The present invention relates to a universal asynchronous receiver/transmitter (UART) and, more particularly, to a UART which supports baudrates higher than 115,200 bps (bits per second) and maintains software and hardware backward compatibility.
Computers such as PCs (personal computers) have serial ports, which are used for bringing data into and out of the computer. The serial port is used for data movement on a channel which requires that one bit be sent (or received) after another, i.e. serially. The UART is typically a device that performs the parallel-to-serial conversion of digital data to be transmitted and the serial-to-parallel conversion of digital data that has been received. The UART converts the incoming serial data from devices such as a modem (or whatever else is connected to the serial port) into the parallel form which the computer handles. The UART also performs the opposite operation by converting the computer's parallel data into serial data suitable for asynchronous transmission.
Prior hardware implementations of the UART include the National Semiconductor 8250 UART which was incorporated with the IBM Personal Computer. The 8250 was limited to 9600 baud maximum rate and was later replaced with the 16450, which has the same architecture as the 8250 but has a higher maximum baud specification. Both of the chips have only a one byte buffer. Therefore, the one byte buffer must be serviced immediately by the CPU; otherwise, interrupt overruns will result. Further, the one byte buffer may slow down the transmission of high-speed data, particularly when using a multitasking program. The 16450 was thereafter replaced by the 16550, which has two 16 byte buffers, one buffer each for incoming and outgoing data, thereby allowing a longer interrupt response time. If interrupt response time is not considered, both 16450 & 16550 UARTs can support baudrates of up to 115,200 bps.
In addition, modems used in conjunction with a UART may be utilized to download data at a rate of up to 56,000 bits/second in accordance with ITU-T Recommendation V.90, the contents of which are incorporated herein. These modems that employ data compression may require an input data rate above 115,200 bps.
Efforts were made to break the baudrate bottleneck of 115,200 bps. However, prior solutions failed to solve both the hardware and software compatibility problems. For instance, one might attempt to simply increase the external clock used for the timing of the UART. Conventional external clocks used for timing of UARTs are 1.8432 MHz. The clock output is generated by using a crystal frequency rated for 1.8432 MHz in combination with a clock generator. Increasing the frequency of the crystal can increase the speed of the UART. However, there are both hardware and software problems associated with simply replacing the crystals. First, there is a hardware problem in terms of physically replacing the existing external clock. In upgrading a conventional UART, the previous external clock must be physically replaced within the circuit board within the computer with the higher speed external clock. This switching of external clocks may prove difficult. Second, there is a software incompatibility problem associated with the increased speed of the external clocks. The current UART software is not designed to handle such upgrades.
As another example of an attempt to increase the speed of the UART, StarTech's ST16650 uses MCR.b7 (Modem Control Register Bit 7) as a clock switch to control the generation of two different clock frequencies to the Baudrate Divisor circuit. There are two major drawbacks of this approach. First, it is not compatible with current Serial Communication software. Second, the limitation of the Modem Control Register Bit 7 leaves no room for future speed expansion.
Accordingly it is desirable to have an improved UART which supports baudrates higher than 115,200 bps, and maintains full software and hardware backward compatibility, so current software will still work at baudrates up to 115,200 bps, and leave enough room for future speed expansion.